3 files changed, 14 insertions, 5 deletions
diff --git a/source/xi_lib/hardcoded.ml b/source/xi_lib/hardcoded.ml
index 314fa1f..37cf1d7 100644
--- a/source/xi_lib/hardcoded.ml
+++ b/source/xi_lib/hardcoded.ml
@@ -35,10 +35,6 @@ let preamble = String.concat "\n"
   ; "   add $sp, $sp, 4"
   ; "   jr $ra"
   ; ""
-  ; "_xi_length:"
-  ; "   lw $v0, -4($a0)"
-  ; "   jr $ra"
-  ; ""
   ; "_xi_concat:"
   ; "   # t0 = lhs"
   ; "   # t1 = rhs"
@@ -119,4 +115,4 @@ let preamble = String.concat "\n"
   ; "   jr $ra"
   ; ""
   ; ""
-  ]
\ No newline at end of file
+  ]
diff --git a/source/xi_lib/iface.ml b/source/xi_lib/iface.ml
index 04658e0..6f139f6 100644
--- a/source/xi_lib/iface.ml
+++ b/source/xi_lib/iface.ml
@@ -64,6 +64,12 @@ module type CALLCONV = sig
 
 end
 
+module type REGISTER_COALESCING = sig
+
+  val coalesce: Ir.procedure -> Ir.RegGraph.t -> Ir.reg list -> bool
+
+end
+
 module type REGISTER_ALLOCATOR = sig
 
   val regalloc: Ir.procedure -> register_mapping
@@ -168,6 +174,8 @@ module type COMPILER_TOOLBOX = sig
   module Spilling : SPILLING
 
   module ReachabilityAnalysis : REACHABILITY_ANALYSIS
+
+  module RegisterCoalescing: REGISTER_COALESCING
 end
 
 
diff --git a/source/xi_lib/plugin.ml b/source/xi_lib/plugin.ml
index 33e6e4e..7069924 100644
--- a/source/xi_lib/plugin.ml
+++ b/source/xi_lib/plugin.ml
@@ -39,6 +39,9 @@ module type MAKE_MIPS_LOWER = functor (T:COMPILER_TOOLBOX) -> MIPS_LOWER
 
 module type MAKE_SPILLING = functor () -> SPILLING
 
+module type MAKE_REGISTER_COALESCING = functor () -> REGISTER_COALESCING
+
+
 module type PLUGIN = sig
 
   val version: string
@@ -82,4 +85,6 @@ module type PLUGIN = sig
   val make_spilling: (module MAKE_SPILLING) option
 
   val make_reachability_analysis: (module MAKE_REACHABILITY_ANALYSIS) option
+
+  val make_register_coalescing: (module MAKE_REGISTER_COALESCING ) option
 end
\ No newline at end of file