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author | Paweł Dybiec <pdybiec@stud.cs.uni.wroc.pl> | 2018-12-23 17:09:57 +0100 |
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committer | Paweł Dybiec <pdybiec@stud.cs.uni.wroc.pl> | 2018-12-23 17:09:57 +0100 |
commit | 3c2d40f55db9527d35b7ef2f1a25dfc82a19a842 (patch) | |
tree | 93f065f71be707433c60f13f2f161a97a0be472c /source/xi_lib/iface.ml | |
parent | While (diff) |
Start of regalloc
Diffstat (limited to 'source/xi_lib/iface.ml')
-rw-r--r-- | source/xi_lib/iface.ml | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/source/xi_lib/iface.ml b/source/xi_lib/iface.ml index 04658e0..6f139f6 100644 --- a/source/xi_lib/iface.ml +++ b/source/xi_lib/iface.ml @@ -64,6 +64,12 @@ module type CALLCONV = sig end +module type REGISTER_COALESCING = sig + + val coalesce: Ir.procedure -> Ir.RegGraph.t -> Ir.reg list -> bool + +end + module type REGISTER_ALLOCATOR = sig val regalloc: Ir.procedure -> register_mapping @@ -168,6 +174,8 @@ module type COMPILER_TOOLBOX = sig module Spilling : SPILLING module ReachabilityAnalysis : REACHABILITY_ANALYSIS + + module RegisterCoalescing: REGISTER_COALESCING end |